In integrated circuits, transistors are made on a semiconductor substrate and connected together using integrated circuit interconnects. This process is performed using a number of different photolithographic, deposition, and removal processes to create contacts to the transistors, trenches to the contacts, and vias interconnecting the trenches where there are more than one level of channels.
Generally, a device dielectric layer is deposited over the transistors, openings are formed through the device dielectric layer down to transistor junctions and gates, and the openings are filled with a conductive metal to form contacts.
In one technique called the “single damascene” process, the formation of the first trenches starts with the deposition of a thin first trench stop layer over the device dielectric layer. The first trench stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the contacts. The photoresist is then removed.
A first trench dielectric layer is formed over the first trench stop layer. Where the first trench dielectric layer is of an oxide material, such as silicon oxide (SiO2) or carbon doped oxide (SiCONH), the first trench stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched. The first trench dielectric layer is then subject to further photolithographic process and etching steps to form first trench openings in the pattern of the first channels. The photoresist is then removed.
A thin adhesion layer is deposited on the first trench dielectric layer over the entire semiconductor wafer and lines the first trench openings to ensure good adhesion of subsequently deposited material to the first trench dielectric layer. High conductivity metals, such as copper (Cu), diffuse easily through dielectric materials such as silicon oxide ad silicon nitride. This diffusion can result in a conductive buildup and cause short circuits in the integrated circuits. To prevent diffusion, a diffusion barrier is deposited on the adhesion layer.
For conductor materials, such as copper, which are deposited by electroplating, a seed layer is deposited on the barrier layer and lines the barrier layer in the first trench openings to act as an electrode for the electroplating process.
A first conductor material is electroplated on the seed layer and fills the first trench opening. The first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
A chemical-mechanical polishing/planarization (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first trench dielectric layer so the materials and layers are coplanar with the dielectric layer. The CMP process leaves the first conductor “damascened” in the first trench dielectric layer to form the first channels. When a thin dielectric layer is placed over the first trenches as a final layer, it is called a “capping” layer and the single damascene process is completed. When the layer is processed further for placement of additional trenches over it, the layer is a via stop layer.
In another technique called the “dual damascene” process, vias and trenches are formed at the same time, generally over a completed single damascene process series of first channels. Effectively, two levels of trenches of conductor materials in vertically separated planes are separated by a dielectric layer and interconnected by the vias.
The dual damascene process starts with the deposition of a thin via stop layer over the first trenches and the first trench dielectric layer. The via stop layer is an etch stop layer which is subject to photolithographic processing using a photoresist and anisotropic etching steps to provide openings to the first channels. The photoresist is then removed.
A via dielectric layer is formed over the via stop layer. The via dielectric layer is then subject to further photolithographic process using a photoresist and etching steps to form the pattern of the vias. The photoresist is then removed.
A second trench dielectric layer is formed over the via dielectric layer. The second trench dielectric layer is then subject to further photolithographic process and etching steps to simultaneously form second trench and via openings in the pattern of the second trenches and the vias. The photoresist is then removed.
A thin adhesion layer is deposited on the second trench dielectric layer and lines the second trench and the via openings. A barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second trench openings and the vias.
For conductor materials such as copper and copper alloys, a seed layer is deposited on the barrier layer and lines the barrier layer in the second trench openings and the vias. A second conductor material is electroplated on the seed layer and fills the second trench openings and the vias.
A CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second trench dielectric layer to form the second channels. When a layer is placed over the second trenches as a final layer, it is called a “capping” layer and the dual damascene process is completed.
The layer may be processed further for placement of additional levels of trenches and vias over it. Individual and multiple levels of single and dual damascene structures can be formed for single and multiple levels of trenches and vias.
A problem exists in forming very thin layers of a uniform thickness for integrated circuits.
A problem occurs with high resistance in the interconnects with decreasing size which reduce the advantage of using high conductivity materials, such as copper, which are desirable for high speed and high reliability interconnections.
A problem occurs with proper deposition on porous ultra low dielectric constant materials coming into use.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.